1. Field of Invention
The present invention is relating to a method of fabricating of gate dielectric layer and semiconductor device. In particular, it is relating to a method of fabricating gate dielectric layer and semiconductor device capable of improving the semiconductor device operating efficiency.
2. Description of Related Art
The conventional technology of fabricating method for gate dielectric layer of metal oxide semiconductor device includes using ion implantation for forming a well inside a substrate. Afterwards, a rapid thermal annealing process is performed on the substrate to compensate for the lattice defects created during ion implantation. Then a cleaning process is conducted. The gate dielectric layer is then formed on top of the substrate.
Because the rapid thermal annealing process is conducted prior to the cleaning process without the removing of the primary oxide layer; it has poorer compensation effectiveness for lattice defect, thus the subsequent quality for gate dielectric layer formed on top of the substrate is reduced.
In addition, during the semiconductor device fabricating process, the device activity is increasing continuously, and at the same time, the gate width is becoming smaller. In the case of the shrinking gate width, the use of conventional technology and method for making gate dielectric layer is unable to increase the on-current for the semiconductor device.